While we have a strong presence in ASIC and Board design, our strength is in FPGA design. We are specialised in FPGA design and focused on Xilinx FPGAs. We have successfully delived over 20 full-cycle FPGA projects in the past where each one was distingushed by its superiority and exceeded client expectations, and even Xilinx limits.
With the rare capabilities of running fully utilized, large size FPGAs at 470MHz system clocks, we are dedicated to provide complete, turnkey FPGA design services. Our years of combined experince in Software, data communication and Hardware design gives us the edge to deliver an entire System on Chip (Zynq) in house with superior futures.
Our FPGA Project Management Template is hardened, optimized and tailored for FPGA Projects during years of FPGA design and eliminates the guessing, discovering, learning curve, process improving, correcting, recovering, reexecuting, or respinning efforts for us and our clients.
Client Management Systems
With ZXZYZ DOS Package, client's product can be accessed over internet or a local network. ZXZYZ DOS Package converts the client product to a ready to go Internet of Things (IoT) product.
DOS (Domain Operating System)
ZXZYZ DOS Package turns client FPGA to a complete internet domain host. This allows the FPGA functionality to be accessed from anywhere and any device online. It is as simple as browsing the FPGA domain site configuration, monitor, or service pages. The DOS package real-time support gives the client capability to monitor hardware systems online. The ZXZYZ DOS package helps client to bring thir system online with minimal design work. DOS package is ready to go product, just add FPGA parameters to the web pages.
- HTTP, WebSocket
- Apache Server, Mail Server
OS (Ubuntu 17)
ZXZYZ Template includes the latest Ubuntu Software for the client. ZXZYZ handles all the upgrade, maintenance and integrity work for Ubunutu in the Template. ZXZYZ enables clients to focus on their work rather than acquiring expertise and investing time for maintenance.
ZXZYZ designs Linux kernel drivers for the clients, based on the FPGA memory map, DMA, and streaming requirements. ZXZYZ drivers can be installed at run time or included in the Linux Kernel compilation.
Linux Kernel (4.12), Real-time Linux Kernel (4.11)
Pre-built Linux Kernel often does not work or not optimized for the clients boards. Linux kernel should be configured and compiled based on available memory and peripherals. ZXZYZ offers customization of Linux Kernel based on client requirements. ZXZYZ also provides full support for kernel upgrading process.
ZXZYZ will configure, compile U-boot and build Board Support package according to client requirements. Optionally ZXZYZ can entirely eliminate U-Boot to have a smaller print BSP in both storage and RAM.
FSBL is usually provided by the vendor. ZXZYZ can customize the FSBL according to client requirements. ZXZYZ creates the BSP for the client board.
We provide AXI connection modules for the clients that already has an FPGA product and want to migrate to Zynq environment. We will connect any bus to Processing system and our Template will handle everything beyond.
HDL (Verilog, VHDL)
ZXZYZ designs Verilog and VHDL modules with very strict gudelines for efficiency, predictibility, consistency and optimization. ZXZYZ is super conscious about HDL quality. ZXZYZ designs HDL specially tailored and optimized for ASIC Vendor library and routing capabilities or specific FPGA device.
ZXZYZ also offers re-design service for the exisitng HDL that can not meet timing or unpredictable behivaour. ZXZYZ has proudly delivered fastest FPGA products globally.
Regardless of what methodology and tools used, the core of simulation activity is to verify all normal and abnormal cases, not single point but complete ranges and leave no bug to the lab verifciation stage.
With todays complicated packet processing FPGAs, testing the practicaly infinite cases can only be acheved by expert developed test environment.
ZXZYZ develops smart automated, and sophisticated test benches and cases that ensures that not only requirements but all the possible cases within and out of ranges are tested.
With ZXZYZ's automated, self generating, self moitoring test environment, full regression can be run througout the project.
Clear structure and dependency tree of the ZXZYZ test benches, the tests can be run long after the project is completed with minimal intervention.
Our success rate for plug and play in the lab is %100 for the products that we verified using ZXZYZ test environment and methodology.
ZXZYZ is commited to deliver products where the lab stage is only used for characterization of the system not debugging. Our goal is to improve overall product by catching missing or inconsistent requirements, and design flaws aside from coding bugs during the simulatiuon stage.
For most projects the Synthesis stage is a push button process with a few constraints. ZXZYZ knows that extreme high clock frequencies can be achieved by designing speed-aware HDL, compartmentalization of HDL properly, constraining correctly, and guiding the place and route process. ZXZYZ creates constraints so that the syntheis tool has minimized decisions for how to implement HDL. This allows additional control in place route precess which enables extreme high clocks to be possible even for large and fully utilize FPGAs.
Mapping is usually an unnotticed stage in FPGA development. However in high speed and high utilization projects, the designers can help the mapper or reduce the scope of mapper by using vendor primitives in the HDL stage. ZXZYZ designers makes sure the HDL source is well implemented so that mapper stage is successful and mapper output predictable. Predictablilty is very important as many constraints only apply to mapper output for extreme high speed projects.
Place and Route
In most projects place and route is left to the tools with no or minimal area constraints in block level. This is not the case for extreme high system clock speeds. Constraints should be as detailed as all DSPs and flops placed, and critical routing is locked manually. This can only be done by a place route expert who also knows the source HDL inside out. ZXZYZ provides this expertize to help clinet meet all the timing requirements consistently and repeatedly.
Bit file editing
Very few in the industry goes this far. ZXZYZ utilizes tools such as FPGA editor very fluently to make improvements and modifications. This allows ZXZYZ to design even faster FPGAs. Another huge advantege is to to last minute surgeries or chagne the behaviour and functionality of legacy FPGA bit files where no source is available.
Bit file generation for Full or Partial configuration
While bit file generation is usually the simplest and shotest stage, it can cost weeks in lab if not properly configured. ZXZYZ ensures client bit files are generated correctly matching the board design. Partial configuration bit file generation is not very different. However it requires significant expertize to architect the HDL to make partial configuration work without a glitch. ZXZYZ provides expertize that ensures the client partial configuration requirements are met successfully.